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EM MICROELECTRONIC - MARIN SA
EM6151
Low Power Windowed Watchdog with Reset, Sleep Mode Functions
Description
The EM6151 offers a high level of integration by combining voltage monitoring and software monitoring using a windowed watchdog. A comparator monitors the voltage applied at the VIN input comparing it with an internal voltage reference VREF. The power-on reset function is initialized after VIN reaches VREF and takes the reset output inactive after a delay TPOR depending on external resistance ROSC. The reset output goes active low when the VIN voltage is less than VREF. The RES and EN outputs are guaranteed to be in a correct state for a supply voltage as low as 1.2 V. The watchdog function monitors software cycle time and execution. If software clears the watchdog too quickly (incorrect cycle time) or too slowly (incorrect execution) it will cause the system to be reset. For enhanced security, the watchdog must be serviced within an "open" time window. During the remaining time, the watchdog time window is "closed" and a reset will occur should a TCL pulse be received by the watchdog during this "closed" time window. The ratio of the open/closed window is either 33%/67% or 67%/33%. The system ENABLE output prevents critical control functions being activated until software has successfully cleared the watchdog three times. Such a security could be used to prevent motor controls being energized on repeated resets of a faulty system. When the microcontroller goes in stand-by mode or stops working, no signal is received on the TCL input of the EM6151 (version 55) and it goes into a stand-by mode in order to save power (CAN-bus sleep detector).
Features
Low quiescent current 35 A -40C to +125C temperature range Windowed watchdog with an adjustable time windows, guaranteeing a minimum time and a maximum time between software clearing of the watchdog Time base accuracy 8% (at 100ms) Voltage reference accuracy 3% Sleep mode function (V55) Adjustable threshold voltage using external resistors Adjustable power on reset (POR) delay using one external resistor Open-drain active-low RESET output Reset output guaranteed for regulated output voltage down to 1.2 V System ENABLE output offers added security Qualified according to AEC-Q100 Green SO-8 package (RoHS compliant)
Applications
Automotive systems Industrial Home security systems Telecom / Networking Computers Set top boxes
Typical Operating Configuration
Selection Table
Part Number VREF Closed Window Open Window CAN-bus sleep detector
VDD
VDD
100nF
Microprocessor
EM6151
ROSC ROSC VSS VIN TCL RES EN
R1
EM6151V30 EM6151V50 EM6151V53 EM6151V55
1.17 V 1.52 V 1.52 V 1.275 V
67% 67% 33% 67%
33% 33% 67% 33%
No No No
I/O RES I/O R2 GND
Yes
Please refer to Fig. 4 for more information about the open/closed window of the watchdog.
Fig. 1
Copyright (c) 2005, EM Microelectronic-Marin SA rev. B / 06.06
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EM6151
Ordering Information
Part Number EM6151V30SO8A+ EM6151V30SO8B+ EM6151V50SO8A+ EM6151V50SO8B+ EM6151V53SO8A+ EM6151V53SO8B+ EM6151V55SO8A+ EM6151V55SO8B+ Version V30 V50 V53 V55 VREF 1.17 V 1.52 V 1.52 V 1.275 V Package SO-8 SO-8 SO-8 SO-8 Delivery Form Stick, 97 pcs Tape & Reel, 2500 pcs Stick, 97 pcs Tape & Reel, 2500 pcs Stick, 97 pcs Tape & Reel, 2500 pcs Stick, 97 pcs Tape & Reel, 2500 pcs Package Marking 6151030 6151050 6151053 6151055
Note: the "+" symbol at the end of the part number means that this product is RoHS compliant (green). For version V30, please contact EM Microelectronic.
Pin Assignment and Description
SO8 1 2 3 4 5 6 7 8 Name
EN
RES
Function Push-pull active low enable output Open drain active low reset output. RES must be pulled up to VDD even if unused Watchdog timer clear input signal GND terminal No connect Supply voltage ROSC input for RC oscillator tuning Voltage comparator input
SO8
EN RES TCL
1 2 3 4 8 7 6 5
VIN ROSC VDD NC
TCL
VSS NC VDD ROSC VIN
EM6151
VSS
Block Diagram EM6151
Enable Logic
EN
Voltage Reference VIN
VREF
Comparator
+
Reset Control
RES
ROSC
Current Controlled Oscillator
Timer
Open drain output RES
TCL
Fig. 2
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EM6151
Absolute Maximum Ratings
Parameter Max. voltage at VDD Max. voltage at any signal pin Min. voltage at any signal pin Storage temperature ESD According to MIL-STD-883C method 3015.7 Symbol VDDMAX VMAX VMIN TSTO VSmax Conditions VSS + 7.0V VDD + 0.3V VSS - 0.3V -65 to +150 C 2000V
Table 1
Operating Conditions
Parameter Operating junction temperature Supply voltage
RES and EN guaranteed
Symbol Tj VDD VDD VIN ROSC
Min. -40 1.2 1.2 0 10
Max. +125 5.5
Units C V V
(note 1) Comparator input voltage RC-oscillator programming
VDD 1000
V k
Table 2
Stresses above these listed maximum ratings may cause permanent damages to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
Handling Procedures
This device has built-in protection against high static voltages or electric fields; however, it is advised that normal precautions be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the voltage range. At any time, all inputs must be tied to a defined logic voltage level.
Electrical Characteristics
VDD = 5.0V, Tj = -40 to +125C, unless otherwise specified Parameter Supply current Supply current in standby mode and sleep mode for V55 RES and EN Output Low Voltage
EN
Symbol IDD IDD VOL
Output High Voltage TCL Input Low Level TCL Input High Level Leakage current Comparator reference (note 2)
VOH VIL VIH ILI VREF
Test Conditions ROSC = 100k VIN and TCL = VDD, O/PS 1M to VDD ROSC = don't care, TCL = VDD, VIN =0V VDD = 4.5 V, IOL = 8 mA VDD = 2.0 V, IOL = 4 mA VDD = 1.2 V, IOL = 0.5 mA VDD = 4.5 V, IOH= -1 mA VDD = 2.0 V, IOH= -100 A VDD = 1.2 V, IOH= -20 A
Min.
Typ. 35 25 0.25 0.2 0.04 4.1 1.9 1.05
Max. 60 50 0.45 0.4 0.2
Units A A V V V V V V V V A V V V V mV M
Table 3
3.5 1.8 0.9 VSS 2.5 1.135 1.475 1.475 1.235
0.5 VDD 0.05 1.170 1.520 1.520 1.275 2 100 1.205 1.565 1.565 1.315
VSS VTCL VDD Version V30 (replaces V6130) Version V50 (replaces V6150) Version V53 Version V55 (replaces V6155)
Comparator hysteresis (note 2) VIN input resistance
VHY RVIN
Note 1: Note 2:
RES must be pulled up externally to VDD even if it is unused. ( RES and EN are used as inputs by EM test) the comparator reference is the power-down reset threshold. The power-on reset threshold equals the comparator reference voltage plus the comparator hysteresis (see Fig. 5).
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EM6151
Timing Characteristics
VDD = 5.0 V, Tj = -40 to +125 C, unless otherwise specified Parameter Propagation delay TCL to Output Pins VIN sensitivity Watchdog Reset Pulse Period Version V30 Power-on Reset delay Closed Window Time Open Window Time Watchdog Time Watchdog Reset Pulse Width if no TCL Version V50 Power-on Reset delay Closed Window Time Open Window Time Watchdog Time Watchdog Reset Pulse Width if no TCL Version V53 Power-on Reset delay Closed Window Time Open Window Time Watchdog Time Watchdog Reset Pulse Width if no TCL Version V55 Power-on Reset delay Closed Window Time Open Window Time Watchdog Time Watchdog Reset Pulse Width if no TCL Watchdog Reset Pulse Width in Sleep Mode Watchdog Reset Pulse Period in Sleep Mode Symbol TDIDO TSEN TWDRP TPOR TCW TOW TWD TWDR TPOR TCW TOW TWD TWDR TPOR TCW TOW TWD TWDR TPOR TCW TOW TWD TWDR TWDRS TWDRPS Test Conditions VINhigh=1.1xVREF, VINlow=0.9xVREF TCL inactive ROSC= 116.9 k 1% Min. Typ. Max. 250 500 1 5 20 TCW + TOW+ TWDR 100 80 40 100 2.5 100 80 40 100 2.5 5.0 10 20 20 0.625 100 80 40 100 2.5 3.2 1100 108.3 85.76 42.88 107.2 2.75 108.3 85.76 42.88 107.2 2.75 5.44 10.77 21.54 21.54 0.69 108.3 85.76 42.88 107.2 2.75 3.6 1450 Units ns s ms
91.6 74 37 92.5 2.25 91.6 74 37 92.5 2.25 4.57 9.24 18.48 18.48 0.56 91.6 74 37 92.5 2.25 2.8 750
ms
ROSC= 121.6 k 1%
ms
ROSC = 23.2 k 1%
ms
ROSC = 107.5 k 1%
ms
ROSC off; RINT=1M TCL inactive
Table 4
For different values of TWD and ROSC, see figures 9 to 12.
Timing Waveforms
Watchdog Timeout Period
Version V50:
TWD
For ROSC=121.6 kOhm
Version V53:
TWD
For ROSC=23.2 kOhm
TCW (closed window)
TOW (open)
TCW (closed)
TOW (open)
Watchdog timer reset
80
120 Time [ms] Watchdog timer reset
10
30 Time [ms]
( V30, V50 and V55 have similar ratios for T CW and TOW )
Fig. 4
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EM6151
Voltage Monitoring
Conditions: VDD > 3V No timeout
VIN VREF VHY
TSEN TSEN TSEN TSEN
TPOR
TPOR
RES
Fig. 5
Timer Reaction
Conditions: VIN > VREF after power-up sequence
TCW TCW TTCL TCW + TOW TCW + TOW TOW TCW TCW + TOW TTCL
TCL
RES
TWDR 1 2 3
EN
3 correct TCL services EN goes active low - Watchdog timer reset
Timeout
Fig. 6
Combined Voltage and Timer Reaction
VIN VREF
TPOR TOW TCW+TOW TTCL TCW
Condition: VDD > 3V
TCL
RES
EN
1
2
3
TCL too early - Watchdog timer reset
3 correct TCL services EN goes active low
Fig. 7
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EM6151
Functional Description
VIN Monitoring The power-on reset and the power-down reset are generated as a response to the external voltage level applied on the VIN input. The threshold voltage at which reset is asserted or released (VRESET) is determined by the external voltage divider between VDD and VSS, as shown on Fig. 8. A part of VDD is compared to the internal voltage reference. To determine the values of the divider, the leakage current at VIN must be taken into account as well as the current consumption of the divider itself. Low resistor values will need more current, but high resistor values will make the reset threshold less accurate at high temperature, due to a possible leakage current at the VIN input. The sum of the two resistors (R1 + R2) should stay below 500 k. The formula is: VRESET = VREF x (1 + R1/R2). Example: choosing R1 = 200 k and R2 = 100 k gives VRESET =4.56 V (typical) for version V50 and V53. At power-up the reset output ( RES ) is held low (see Fig. 5). When VIN becomes greater than VREF, the RES output is held low for an additional power-on-reset (POR) delay TPOR (defined with the external resistor connected at ROSC pin). The TPOR delay prevents repeated toggling of RES even if VDD voltage drops out and recovers. The TPOR delay allows the microprocessor's crystal oscillator time to start and stabilize and ensures correct recognition of the reset signal to the microprocessor. The RES output goes active low generating the powerdown reset whenever VIN falls below VREF. The sensitivity or reaction time of the internal comparator to the voltage level on VIN is typically 3 s. Timer Programming The on-chip oscillator allows the user to adjust the power-on reset (POR) delay TPOR and the watchdog time TWD by changing the resistor value of the external resistor ROSC connected between the pin ROSC and VSS (see Fig. 8). The closed and open window times (TCW and TOW) as well as the watchdog reset pulse width (TWDR), which are TTCL dependent, will vary accordingly. The watchdog time TWD can be obtained with figures 9 to 12 or with the Excel application EM6151ResCalc.xls available on EM website. TPOR is equal to TWD with the minimum and maximum tolerances increased by 1% (For Version 53, TPOR is one fourth of TWD). Note that the current consumption increases as the frequency increases. CAN-Bus Sleep Mode Detector (version 55) When the microcontroller goes into a standby mode, it implies that it does not send any pulses on the TCL input of the EM6151. After three reset pulse periods (TCW + TOW + TWDR) on the RES output, the circuit switches on an internal resistor of 1 M, and it will have a reset pulse of typically 3 ms every 1 second on the RES output. When a TCL edge (rising or falling) appears on the TCL input or the power supply goes down and up, the circuit switches to the ROSC. Watchdog Timeout Period Description The watchdog timeout period is divided into two periods, a closed window period (TCW) and an open window period (TOW), see Fig. 4. If no pulse is applied on the TCL input during the open window period TOW, the RES output goes low for a time TWDR. When a pulse is applied on the TCL input, the cycle is restarted with a close window period. For example if TWD = TPOR = 100ms, TCW = 80 ms, TOW = 40ms and TWDR = 2.5ms. When VIN recovers after a drop below VREF, the pad RES is set low for the time TPOR during which any TCL activation is disabled. Timer Clearing and RES Action The watchdog circuit monitors the activity of the processor. If the user's software does not send a pulse to the TCL input within the programmed open window timeout period a short watchdog RES pulse is generated which is equal to TWDR (see Fig. 6). With the open window constraint, new security is added to conventional watchdogs by monitoring both software cycle time and execution. Should software clear the watchdog too quickly (incorrect cycle time) or too slowly (incorrect execution) it will cause the system to be reset. If software is stuck in a loop which includes the routine to clear the watchdog then a conventional watchdog would not make a system reset even though the software is malfunctioning; the circuit would make a system reset because the watchdog would be cleared too quickly. If no TCL signal is applied before the closed and open windows expire, RES will start to generate square waves of period (TCW + TOW + TWDR). The watchdog will remain in this state until the next TCL falling edge appears during an open window, or until a fresh power-up sequence. The system enable output, EN , can be used to prevent critical control functions being activated in the event of the system going into this failure mode (see section "Enable- EN Output"). The RES output must be pulled up to VDD even if the output is not used by the system (see Fig 8). Combined Voltage and Timer Action The combination of voltage and timer actions is illustrated by the sequence of events shown in Fig. 6. On power-up, when the voltage at VIN reaches VREF, the power-on-reset, POR, delay is initialized and holds RES active for the time of the POR delay. A TCL pulse will have no effect until this power-on-reset delay is completed. When the risk exists that TCL temporarily floats, e.g. during TPOR, a pull-up to VDD is required on that pin. After the POR delay has elapsed, RES goes inactive and the watchdog timer starts acting. If no TCL pulse occurs, RES goes active low for a short time TWDR after each closed and open window period. A TCL pulse coming during the open window clears the watchdog timer. When the TCL pulse occurs too early (during the closed window), RES goes active and a new timeout sequence starts. A voltage drop below the VREF level for longer than typically 3s overrides the timer and immediately forces RES active and EN inactive. Any further TCL pulse has no effect until the next power-up sequence has completed.
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EM6151
Enable - EN Output The system enable output, EN , is inactive always when RES is active and remains inactive after a RES pulse until the watchdog is serviced correctly 3 consecutive times (i.e. the TCL pulse must come in the open window). After three consecutive services of the watchdog with TCL during the open window, the EN goes active low. A malfunctioning system would be repeatedly reset by the watchdog. In a conventional system critical motor controls could be energized each time reset goes inactive (time allowed for the system to restart) and in this way the electrical motors driven by the system could function out of control. The circuit prevents the above failure mode by using the EN output to disable the motor controls until software has successfully cleared the watchdog three times (i.e. the system has correctly re-started after a reset condition).
Typical Application
Regulated Voltage (5V) VDD
EM6151
ROSC VIN
TCL
100k
R1
Address decoder
Microprocessor
RES
RES
VSS
EN
R2
EN
Motor controls GND
Fig. 8
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EM6151
V30 ROSC Coefficient versus TWD at VDD= 5.0V and Tj=-40 to +125C
1.44
1.38
Max
1.32 Rosc Coefficient [kOhm/ms]
1.26
1.20
Typ
1.14
1.08
Min
1.02
0.96 10 100 Twd [ms] 1000
Fig. 9
V50 ROSC Coefficient versus TWD at VDD= 5.0V and Tj=-40 to +125C
1.44
1.38
Max
1.32 Rosc Coefficient [kOhm/ms]
1.26
1.20
Typ
1.14
1.08
Min
1.02
0.96 10 100 Twd [ms] 1000
Fig. 10
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EM6151
V53 ROSC Coefficient versus TWD at VDD= 5.0V and Tj=-40 to +125C
1.46
1.40
Max
1.34 Rosc Coefficient [kOhm/ms]
1.28
1.22
Typ
1.16
1.10
Min
1.04
0.98 10 100 Twd [ms] 1000
Fig. 11
V55 ROSC Coefficient versus TWD at VDD= 5.0V and Tj=-40 to +125C
1.34
1.28
Max
1.22 Rosc Coefficient [kOhm/ms]
1.16
1.10
Typ
1.04
0.98
Min
0.92
0.86 10 100 Twd [ms] 1000
Fig. 12
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EM6151
Package Information
Dimensions of 8-pin SOIC Package
D C L H Dimensions in mm Min Nom Max A 1.35 1.63 1.75 A1 0.10 0.15 0.25 B 0.33 0.41 0.51 C 0.19 0.20 0.25 D 4.80 4.94 5.00 E 3.80 3.94 4.00 e 1.27 H 5.80 5.99 6.20 L 0.40 0.64 1.27 E 0 - 8
A1 B e
A
4
3
2
1
5
6
7
8
Fig. 13
EM Microelectronic-Marin SA (EM) makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in EM's General Terms of Sale located on the Company's web site. EM assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of EM are granted in connection with the sale of EM products, expressly or by implications. EM's products are not authorized for use as components in life support devices or systems.
SUBJECT TO CHANGE WITHOUT NOTICE
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